Intel Pentium D 945 3.4 GHz/4 Mb/800 (SL9QQ) s775

Артикул: 3945rd

100 грн.

Наличие: нет в наличии

Модель: Pentium_D_945_SL9QQ

Количество − +

Описание из: http://www.cpu-world.com/sspec/SL/SL9QQ.html

SL9QQ specifications

General information
Type	CPU / Microprocessor
Family	Intel Pentium D
Processor number ?	945
Part number	HH80553PG0964MN BX80553945
Frequency (GHz) ?	3.4
Bus speed (MHz) ?	800
Clock multiplier ?	17
Package type	775-Land FC-LGA6
Socket type	Socket 775 (LGA775)
Architecture / Microarchitecture / Other
CPUID	0F65h
Core stepping	D0
Processor core	Presler
Manufacturing technology (micron)	0.065
Number of cores	2
L2 cache size (MB) ?	4
Features	EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ?
Core voltage (V) ?	1.225 - 1.325
Case temperature (°C) ?	63.4
Notes on sSpec SL9QQ
The processor supports the 775_VR_CONFIG_05A (mainstream) guidelines for processors with TDP up to 95 Watt, Iccmax up to 100A, and VID up to 1.4V.

In addition to the SL9QQ S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

Stepping	S-Spec	HH80553PG0964MN	BX80553945	BX80553945R
C1	QRLS	+
C1	SL9QB	+	+	+
D0	SL9QQ	+	+

NOTE: Engineering and qualifications samples are marked with this color

Intel Pentium D 945 SL9QQ

Part number:	HH80553PG0964MN
Measured Frequency:	3396 MHz

Comment:
Submitted by:	CPU-World

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Pentium(R) D CPU 3.40GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	F65
Family:	15 (0Fh)
Model:	6 (06h)
Stepping:	5 (05h)
TLB/Cache details:	Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache

Cache:	L1 data	L1 instruction	L2
Size:	16 KB	12K uops	2 MB
Associativity:	8-way set associative	8-way set associative	8-way set associative
Line size:	64 bytes		64 bytes
Comments:	sectored cache

Instruction set extensions		Additional instructions

MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Enhanced SpeedStep		CPL qualified debug store
		Debug store
		Debugging extensions
		L1 context ID
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control